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Chipset(2,3,4)
Front Side Bus
General(2)
Operation
Page 1
Operating System
Resources(2)


System Operation

A core logic chipset is the nervous system of a computer. The Central Processing Unit is more like the brain. The CPU is responsible for all of the "thinking" but the chipset is responsible for allowing everything to communicate.

Translating

The core logic chipset is basically responsible for the CPU's dirty work. When the CPU sends a memory address for a read, the core logic chipset's job is to find where the memory location is, whether it is in main memory, on the hard drive, or on a peripheral like a video card or serial port. Next, it relays the request in a form which the device can understand. This translation will take 1 clock cycle on most computers. The translation will take up to one cycle for the chipset to process, and if the FSB and System Bus run asynchronously, then another cycle is often needed to correctly time the signals.
Chipset and Memory
One of the many tasks that a chipset has is to provide a way for the CPU to communicate with main memory.

One of the major tasks in memory access is memory support. The core logic chipset is responsible for all of the addressing of memory locations. Remember that the CPU sees memory as a linear storage line. Memory is actually a complex network of 2 dimentional arrays of information which is interleaved between multiple chips on a separate modules. The chipset translates the linear addressing of the CPU to the multiple bank spanning single bit storage method that memory uses.

This means the chipset is also responsible for supporting the different features that different DRAM have, such as Fast Page Mode DRAM's ability to burst consecutive CAS cells without having to resend the RAS address, and Synchronous DRAM's ability to have multiple banks and ability to incremental burst without needing to be sent either RAS or CAS lines. This is not to mention the advanced functions that RDRAM use.

Multipliers And Bus Frequencies
CPU clockspeed is determined by the bus frequency which it is connected to. Because most bus frequencies only are able to operate at speeds up to 133MHz, a multiplier is used. Multipliers and bus frequencies are all generated by a special chip, called a frequency generator. This chip is responsible for the timing of all of the chips on the motherboard, including the CPU. This chip produces a special signal which is referenced by specific devices so that the devices know how fast to operate. All CPU, AGP bus, memory bus, PCI bus, and internal chip operation is controlled by these signals. For simplicity, clock gerators are able to operate with multipliers in 0.5 increments. Most motherboards are capable of supporting multipliers from 5.5 all of the way up to 8.5. These multiplier settings are used by the CPU in conjunction with the CPU's bus frequency. If a CPU is operating on a 100MHz bus, and it has a 6.5 multiplier, the chip knows to operate at 650MHz.
The Front Side Bus
This is the information pathway between the CPU and the core logic chipset. Normally there is nothing else connected on this bus, although some older 486's used a VL-Bus connection, which proved to be unstable and limiting to FSB operations.

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