All RAM, whether it is Static RAM or Dynamic RAM consists of chips. These chips contain 2 dimensional cells of 1 bit each. This means that each single bit cell has an x address and a y address, know as Rows and Columns. For example, a chip with 256 rows and 256 columns contains 65536 cells/bits, for a total of 8192 bytes or 8 kilobytes. Note that there are 8 bits one byte, and 1024 bytes in one kilobyte. Find out more here.

The CPU doesn't see RAM as a 2 dimensional configuration, but as a 1 dimensional or linear arrangement. It is up to the RAM controller and chipset to interpret what location the CPU wants and act as a "translator" between the two devices.

For SRAM, the bandwidth needed for a location in double that of the DRAM. This means more pins, but faster speed.

SRAM
For a SRAM access to take place, a number of things have to occur. The first that needs to take place for a read, the WE, write enable has to be turned off. Because of the notation, this pin is deactivated with a high signal (or a 1), and activated with a low signal (or a 0). This will tell the chip that information is not being written to. If information is to be written or stored to the chip, than this pin needs to be deactivated. Next the chip select pin is activated. This will tell the chip that it is to accept information that is sent to it via the address bus. This pin is used to distinguish between multiple chips because memory is made to share the same bus. Next, the address needs to be sent to the chip. The RAS and CAS address are sent to the chip through the address bus. The SRAM finds and opens the cell specified, and if this was a write cycle it would store the information that is sent to it on its DataIn pin. If a read was specified, than it will output the contents of the cell to the Dataout pin.

DRAM
DRAM access is a little more complicated. The RAS signal is send to the chip via the address bus. Remember that CAS and RAS signals are multiplexed, so they are not sent at the same time. To tell the chip that this address is a RAS signal, the RAS pin is activated. The chip sends the right RAS line to the precharge amps which prepare the row for access. If this is to be a write access, than the Write Enable pin is activated. If this access is to be read only, then the Write Enable pin is deactivated. Once the chip is ready for the CAS location, it is sent it via the same address bus that it received the RAS address. Only difference here is that the RAS pin is deactivated, and the CAS pin is activated. If the RAS line is already charged because the last access used that row, than that is referred to as a Page Hit. If the line is not already charged, than it has to recharge the sense amps before the row can be accessed. This will usually take between 2 to 4 cycles. When the wrong page is open, it is referred to as a Page Miss. If the wrong page is open, it first has to be closed before the correct row can be charged. This will cost another 2 cycles. It is up to the chipset to try and keep the correct rows precharged, because correcting Page Miss can take as much time as a complete Page Hit access would take. For reading, the CAS location is sent to the sence amps which send the contents to the data bus for output. If this was a write, then information is sent to the chip via the data bus to the sense amps which in turn send the data to the correct cell for storage.

As you can see, DRAM access has a few more steps, and access can take a little bit longer. But newer versions allow for pipelining and burst operation which can "cover up" this access time by being able to do multiple access tasks and bank interleaving.

Chip Operation | SIMM, DIMM, & RIMM