Instruction Set Architecture
Early computers were designed to include any processor instructions that the engineers wished to include. This made programming for these specific instructions hard because there was no specific set of instructions that all processors had. Software had to be specifically written for each processor, making code incompatible between most computers. Software was also incompatible between different versions of the same processor.
Along comes the x86 instruction set. This is a standard set of instructions that is included in all consumer PC computers. This made programming for different processors easy. The x86 has been expanded, by the addition of SIMD code, but none of the original instructions have been altered.
CPU Micro-Opts
The x86 specifies what instructions a processor has to include, and what the instructions have to do. It does not specify how the instructions have to be computed. This has allowed the over 10 year old x86 instruction set to evolve with the current processors. Most processors break each x86 instruction down into smaller operations, called micro-ops. These are much simpler, and can be computed faster, resulting in an overall speed increase over the older processors.
RISC Vs CISC
Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC) are two different ways to increase speed. In the beginning, computer memory was slow, and very expensive. To make computers more economical, the complexity was added to the hardware which allowed for more compact code. There were so many instructions, most went unused. The CISC instructions were so complex that they take multiple clock cycles to complete. If a small instruction that takes 3 cycles to process is being processed in one pipeline of a superscalar processor, while another instruction was being processed in another pipeline, a missalignment could occur. If the second istruction took only 1 cycle to complete comparied to the 3 cycle instruction, the resulting code would be out of order. Eary CISC computer frequecies were limited by this timing issue because each instruction had to monitored. There was a constant need for keeping track of instructions so could be reassembled in the same order that it was input. All consumer PC's use CISC processors.
| Instruction | RISC | CISC |
| Multiplication | a X b | a X b |
| Squaring | a X a | a2 |
| Cubing | a X a X a | a3 |
| Processing Time | = | (time/instruction) | x | (instructions/operation) |
| CISC | = | (+1) | x | (1) |
| RISC | = | (1) | x | (+1) |
Apple computers and most high end servers and workstations use RISC processors. In general, RISC processors are superior to CISC processors. With RISC processors, all instructions are 1 cycle, making the need for this monitoring obsolete. RISC was founded later then CISC, when memory was cheaper than processing time, so the bulky CISC ISA was no longer needed. CISC had already a big market, and because software was incompatible between the two, RISC never caught on. Most consumers were unwilling to have to go out and buy all new software for if they wanted a RISC computer. This didn't stop RISC from being accepted into the server market, where performance is more important than money.
RISC processors were designed with simplicity in mind. This means that the RISC processors would naturally be smaller than CISC processors because they would have less transistor logic. To fully exploit the manufacturing process, RISC processors use this extra space to add more registers and buffers on die. What this means is that they are able to keep more information in memory which is faster than L1 cache, and allows more operations to be performed before new information has to be loaded. This is what gives RISC processors their speed. The average workstation RISC processor can calculate more than twice the floating point operations of an equally clocked CISC processor.
The current processors are neither RISC or CISC. Some of today's "RISC" processors actually have more instructions then "CISC" processors, while today's "CISC" processors have included the greater buffer sizes that at one point only RISC processors had.
|