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I-Unit Pipelining - Overview
In the instruction execution section, it showed that an instruction
is executed as a number of steps. While the circuitry is being used to
execute one of these steps, the circuits to perform the other steps go
unused. This circuitry can be used to execute other instructions at the
same time. The executions of these instructions must be staggered so that
two instructions never use the same circuitry at the same time. This staggering
of instructions is referred to as pipelining.
One issue with pipelining is that sometimes, an operation to be performed
is dependent on the result of an instruction further down the pipeline.
To use pipelining, a CPU must detect these dependencies and hold up an
instruction's execution until the result(s) it needs are available. This
holding up of an instruction is called an interlock.
Ideally, pipelining would increase the performance of a processor by
the number of steps needed to execute an instruction. The example pipeline
in the instruction execution section had 6 steps. So theoretically, this
technique would increase the speed by a factor of 6. Although this can
occur for some sequences, required interlocks and miss predicted branches
lower the performance gain.
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