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Instruction Execution I-Unit Pipelining I-Unit Bypassing Die Size Technology Prediction

Example 3 - Add

For this example, we will demonstrate the execution of the following instruction:
1A56
with the following assumptions:
  • The CPU implements the S/370 architecture.
  • The initial values of GPRs 5 and 6 are 11223344 and 12345678 respectively.
The first 8 bits of this instruction are equal to 1A Hex (0001 1010 Binary). For the S/370 architecture, this opcode signifies it's an Add register instruction. It is specified to be an RR format instruction, therefore this instruction consists of the following fields:
Opcode - 1A     R1 - 5     R2 - 6
An Add register adds the contents of the GPRs specified by the R1 and R2 fields of the instruction and stores it in the register specified by R1 field. Note that this instruction writes its result over top of the first source operand. For our sample pipeline, this instruction would be executed as follows:

D-Stage

Examine the first 8 (sometimes 16) bits of the instruction to determine the instruction to be executed. In this case, they are equal to 1A, which in the S/370 architecture indicates it's an Add register instruction.

A-Stage

This stage is used to calculate the EA of any memory based operands. An Add register instruction has no memory based operands, therefore no operation will be performed during this stage.

T-Stage

Used to translate each of the EAs' for memory based operands to their corresponding physical address. Since this instruction has no memory based operands, there are no EA values to be translated. Again, this stage will be a nop for this instruction.

B-Stage

Obtains the source operand(s). An Add register instruction has 2 source operands. The operands are the contents of the GPRs specified by the R1 and R2 fields of the instruction. In this example, the R1 and R2 fields are equal to 5 and 6. Based on the assumptions above, the initial contents of registers 5 and 6 are equal to 11223344 and 12345678. Therefore, the source operands for this example are going to be equal to 11223344 and 123454678.

E-Stage

Calculates the result of the instruction. For an Add register instruction, the result is the sum of the 2 source operands. In this example, the 2 source operands obtained by the B-Stage are 11223344 and 12345678. The sum of those 2 operands is 235689BC.

W-Stage

Writes the result from the E-Stage. For an Add register instruction, the result is stored into the register specified by the R1 field of the instruction. In this case, the result of 235689BC, from the E-Stage, will be written to GPR5.
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