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Instruction Execution I-Unit Pipelining I-Unit Bypassing Die Size Technology Prediction

Example 1 - Loading

For this example, we will demonstrate the execution of the following instruction:
58204060
with the following assumptions:
  • The CPU implements the S/370 architecture.
  • Memory Locations 105060 - 105063 have the values 89, AB, BA, 98.
  • General Purpose Register (GPR) 4 is equal to 00005000.
  • The Operating System has "setup tables" so that the number 100000 (HEX) is added to all of the memory addresses specified by the program to determine the location in physical memory.
In the S/370 architecture, the first 8 bits (sometimes the first 16) of an instruction specify the instruction type. In this case, the first 8 bits are equal to 58 Hex (0101 1000 Binary). During the design of the S/370, this value was assigned as the indication of a Load (L) instruction. The purpose of this instruction is to load a 4 byte value from memory into a specified GPR. A Load instruction is defined to use the RX instruction format. Therefore, the instruction is composed of the following fields:
Opcode - 58     R1 - 2     X2 - 0     B2 - 4     D2 - 060
As specified above, opcode specifies the type of the instruction, in this case, it's a Load instruction. For this format (RX), the R1 field specifies the GPR that the value loaded is to be stored into. The last three fields (X2, B2, D2) are used to generate (produce) the address of where the first byte of the value to be loaded is at. The X2 and B2 fields specify registers that contain the index and base parts of the address unless the field is equal to 0. When the X2 or B2 fields are equal to 0 then it is implied that the corresponding index or base is equal to 0, instead of the contents of GPR0. The last field for address generation is D2. It specifies a displacement for the address generated from the index and base values to the start of the actual operand. The address is calculated by adding the index, base and displacement values together. For this example there is an implied index of 0 since the X2 field is 0, a base of 5000 (the contents of GPR4) and a displacement of 060. With this the address that will be generated for this instruction is 5060. Given the I-Unit pipeline described in this section, this instruction would be executed like this:

D-Stage

Determines the instruction to be executed. This is done by looking at the first 8 (sometimes 16) bits of the instruction. In this case, the first 8 bits are 58, which indicates it's a Load instruction in the S/370 architecture.

A-Stage

Performs Effective Address (EA) generation. This will determine the location of the value to be loaded from memory. For this example, the index and base fields are equal to 0 and 4, respectively so the index is an implied value of 0, while the base comes from GPR4. Based on the assumptions stated above, the contents of GPR4 are equal to 5000. The implied index and base values are added with the displacement value (60) from the instruction to produce an EA of 5060.

T-Stage

Translates the EA to it's equivalent address in physical memory. This is performed based on the values of tables located in memory. The contents of these tables are normally controlled by the operating system. For this example, we assume that these tables have been setup so that the data in physical memory is always located in an address 100000 Hex greater than the EA. In this case, the EA of 5060 is translated to a physical address of 105060.

B-Stage

Obtains the source operand(s). For a Load instruction, there is a single source operand, which is the value to be loaded from memory. For this example, the physical address (determined during the T-Stage) was 105060, so during this stage, the CPU needs to obtain the 4 bytes starting at that address. Based on the assumptions above, the 4 byte value starting at that address is 89ABBA98.

E-Stage

Calculates the result of the instruction. For a Load instruction, the result is the same as the input. This is done by the ALU performing an operation that produces a result as equal to the source operand (e.g.. Add 0). During the B-Stage, an OP1 value of 89ABBA98 was obtained for this instruction. An operation that has no effect on the source will be used to produce the result of 89ABBA98.

W-Stage

Writes the result from the E-Stage (89ABBA98). For a Load instruction, the result is written to the GPR specified by the instruction's R1 field. In this case, it's GPR2. So the value of 89ABBA98 is written into GPR2.
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