Memory is the general term used to describe a way the computer has to store information so as to be able to access it very quickly. In this section, RAM and cache memory will be discussed.
RAM is used by the computer as a way of temporary storage. It makes the information needed by the CPU more accessible than if it were stored in the hard drive. Therefore, this allows the CPU to process information much more quickly. However, this information does not remain in the RAM once the computer is turned off, unlike information stored on a hard drive.
72-pin SIMMs were used in 386s through Pentiums. 386s and 486s used SIMMs individually whereas Pentiums required SIMMs to work in pairs. There were also 30-pin SIMMs but these are too old to be worth any attention. 72-pin SIMM capacity can range from 4MB to 128MB.
DIMM memory is what is used nowadays. There are two types of DIMM: SO (Small Outline) DIMM and 168-pin DIMM. SO DIMM is used in laptops and notebooks for it is on the whole, a reduced version of the 72-pin SIMM. 168-pin DIMM capacity can range from 8MB to 512MB.
DRAM chips are what make up RAM bars. They are attached to a printed circuit board which is then inserted into the corresponding slot. DRAM chip technology then moved on to:
Cache Memory is a high-speed type of memory (on a typical
100-MHz system board, the CPU needs 180 nanoseconds to obtain
information from the RAM whereas it only needs 45 nanoseconds to
obtain information from the cache memory) which accelerates the
processing of information undertaken by the CPU.
Primary cache (or Level 1 cache, L1) is the cache located the
closest to the CPU and is usually internal (built into the
CPU).
Secondary cache (or Level 2 cache, L2) is external (located
outside the CPU).
Before reading this part, you will need to read the section
called Assembler (sub-sections Binary
System through Mathematical Operations in Binary) for some
knowledge concerning bits is required to understand the following
explanations.
SR latches
As shown in the diagram above, there are only two possible states for SR latches. When a pulse is given on the S(et), Q becomes a 1, and when a pulse is given on the R(eset), Q stabilizes on 0.
However, in this design, the latch can change state at any time. It is usually more convenient (for reasons far beyond the scope of this page) for memory to change only at certain times. This problem can be easily solved by connecting the two inputs with a clock circuit and an AND gate each. When this is added to the circuit, the S or the R can only contain a 1 when there is a pulse from the clock. The circuit will look like this:
However, this circuit still presents a problem. The S and the R can still be turned on at the same time causing and unpredictable result. In response to this problem, D latches were developed.
D latches
As you can see in the circuit above, there is only 1 input in
a D latch, the other being replaced with a NOT gate. Therefore
when the input is 1, the other will be 0, and vice-versa. When a
clock is added to this design, a non-corruptible circuit is
achieved.
Each one of these latches provides one bit of memory. As said before memory chips come in different sizes ranging from 8MB (8*2^20 bytes) to 512MB (512*2^20*3 bits). Since one latch can contain one bit, in the 512MB memory chip, there are 1610612000 latches.
If you came here from the assembler section, please feel free to go on to Instructions and Opcodes. [an error occurred while processing this directive]