[an error occurred while processing this directive]
We have mentioned the Arithmetic Logic Unit (ALU) in earlier pages, however we have never gone into its details. The ALU is the part of the microprocessor that handles all boolean and mathematical operations. However, exploring an actual ALU from one of the current microprocessors is too complex for our purposes. Thus, we have taken a more simplified design that, although limited in functionality, will show you the general picture.
It is best for you to first familiarize yourself with the diagram below before reading on, such that you can better understand the rest of this section. If you are somewhat confused by this drawing, there is nothing wrong. We have divided the diagram into three sections: Logical Unit, Decoder, and Full Adder. You can also observe that the inputs are A, B, F0, F1, and Carry In. You can also notice several 3-input AND gates and a 4-input OR gate. They are basically the same as the 2-input gates that were presented earlier, except that the 3-input AND gate only outputs a 1 if all 3 inputs are 1s, and the 4-input OR gate always outputs a 1, except when all inputs are 0s.
The F inputs control the enable lines. As you can see, no matter which of the four possible combinations of F inputs is put in, only one (and each time different) enable line will be "turned on." Thus, the function of the decoder subpart is to figure out which of the 4 operations will be done. The A and B are used as the regular inputs for all operations.
The full adder is nearly the same circuit as the one shown on the Mathematical Operations page. However, all output is ANDed with the corresponding enable line. The logical unit is simply a collection of three boolean operations, AB, A+B, NOT B. As with the full adder, each of their outputs is ANDed with the corresponding enable line. On the very right, all of the outputs are ORed together. However, only one of the four inputs could potentially be a 1 because of the enable lines.
The diagram, however only represents a 1-bit ALU. Most likely, an 8-bit ALU is more convenient for useful operations. To create an 8-bit ALU, this diagram needs to be repeated 8 times, linking the Carry-Out to the Carry-In of the next one each time. This concept has already been introduced with the full adder.
In case you have not fully understood how the ALU works, we will present a sample case. In this sample case, the inputs are A=1, B=0, F0=1, F1=0, and we will not worry about the Carry In. Going to the decoder, we can see that this will enable the third enable line. By following this enable line, we find out that it is going to be ANDed with the NOT, thus we will only explore the NOT (since all the other outputs will be ANDed with 0, automatically producing a 0 output). The NOT takes in only B. Since B is 0, NOT B is 1. When that 1 is ANDed with the enable line, it produces a 1, since both are 1. This then goes to the output, where the 1 is ORed with 3 other 0s. Thus the output will be 1, and the carry out will be 0.
The next section of the assembler page is Memory Storage.[an error occurred while processing this directive]